Description

0.1 Experiment 1 (Analysis and Implementation of a Problem Definition)
0.1.1 Aim
In this experiment, you will implement a circuit design of a solution to a problem.
0.1.2 Problems
You have only 2xAND, 2xOR, and 4xNOT gates at your disposal. The AND and OR gates are binary, i.e. they take exactly two inputs. You are expected to design the circuit which uses the fewest number of gates as possible. Designs with the fewest number of gates will get the highest grades.
During Verilog implementation, you have to use the template source codes we provide.
0.1.3 Preliminary Work
Before the experiment, you should prepare the following materials:
1. Fill the truth table given in the template according to the design requirements.
2. Write the sum of products (SOP) expression for the truth table.
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3. Find the minimized SOP expression by using Boolean theorems and axioms(show your work clearly, minimize the equation you previously found in step 2 using the laws used in class, using exactly one law per line). The minimized expression must also be in SOP form.
4. Write the product of sums (POS) expression for the truth table.
5. Find the minimized POS expression by using Boolean theorems and axioms(show your work clearly, minimize the equation you previously found in step 4 using the laws used in class, using exactly one law per line). The minimized expression must also be in POS form.
6. Draw the circuit for the minimized expression using only binary (which meansit has two inputs) AND, OR, and NOT gates.
7. Fill the gate level verilog code for the circuit chosen at the previous step. You can use the built-in AND, OR, and NOT gates.
8. Write the code for the testbench in order to test all possible input combinations.
9. Verify that the outputs of your implementation is the same as the truth table.
Then, submit the your code, and your report under the name
<StudentID1>_<StudentID2>_PRE1.zip through Moodle. One submission per group is required.