Description

Yunseon Shin
ysshin@postech.ac.kr
Contact the TAs at csed311-ta@postech.ac.kr
Contents
◼ Objectives
◼ Pipelined CPU without control flow instructions
◼ Data Hazard
◼ Assignment
2
Objectives
◼ Understand and implement a pipelined CPU
◼ First implement a pipelined CPU without control flows
3
Labschedule
◼You will be implementing a pipelined CPU without control flow instruction support
̶ Control flow instructions will be implemented in Lab 4-2
Lab4-1 Lab4-2

Pipelined CPU
◼Increase throughput through better HW utilization

5
Datapath(w/ocontrolflowinstrs.)
◼You don’t have to implement control flow instructions now
̶ E.g., JAL, BEQ, …

Update pipelineregisters
◼You need to understand how pipeline registers work
̶ Pipeline registers are updated at rising edge of the clock

Hazard
◼Your implementation should properly resolve:
̶ Data hazard
̶ Structural hazard
• We do not append hardware modules to resolve structural hazard ̶ Control hazard
• We do not implement branch instructions now
Datahazard
◼You need to detect when the data hazard occurs

Datahazard
◼To stall the pipeline, you need to prevent any architectural state update by NOP(s)

Data forwarding
◼ To reduce stalls, you can also implement data forwarding (extra credit)

◼ How to halt CPU?

◼ You need to pipeline the halt signal

◼ Hazard and forwarding
̶ Also, data hazard should be handled properly by stalls or data forwarding

̶ 5-stage pipelined CPU
•Data hazard
− Stall (no extra credit)
− Data forwarding (extra credit +10)
•You don’t have to handle control hazard − Control flow instructions will not be used in this implementation
̶ You need to follow the rules described in lab_guide.pdf
̶ Do not modify these files: top.v, RegisterFile.v, DataMemory.v, and InstMemory.v
̶ Compare total cycles between the single cycle and pipeliend CPU
•Non-control flow input file ̶ How to implement hazard detection?
•When detected?
̶ How to implement data forwarding?
•When forwarded?
◼ File format
̶ .zip file name: Lab4_{team_num}_{student1_id}_{student2_id}.zip ̶ Contents of the zip file (only *.v):
• cpu.v
•…
• Do not include top.v, DataMemory.v, InstMemory.v, and RegisterFile.v

ETC.
◼ In this lab, even if the same register is read from and written to at the same cycle, the internal forwarding mentioned in the textbook is not needed, because the write is done first at the at the negative edge.
18
Questions?