Description

Yunseon Shin
ysshin@postech.ac.kr
Contact the TAs at csed311-ta@postech.ac.kr
Objectives
◼ Understand and implement a pipelined CPU
◼ Implement a pipelined CPU with control flows
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Labschedule
• You will be implementing a pipelinedCPU with control flow instruction support
• Cache will be implemented inLab5
Lab4-1 Lab4-2 Lab5

Datapath (w/control flow instructions)
• Resolve at EXE stage (BEQ, BNE, BLT, BGE, JAL, JALR)
• Miss prediction causes two bubbles

Submission
• 5-stagepipelinedCPU w/ control flow instructions
• Implement your design over lab4-1 implementation
• Control hazard
• Branch prediction (need to flush on misprediction)
• Always not taken (no extra credit) – Does not require BTB
• Always taken (partial extra credit +3) – Require BTB (32 entries)
• 2-bit global prediction (partial extra credit +5) – Require BTB (32 entries)
• Gshare (full extra credit +7) – Require BTB (32 entries)
• The BTB must be initialized as empty
• Youneedtofollowtherulesdescribedinlab_guide.pdf
• Howto handle branch prediction?
• Describe your design of branch predictor
• If you implement 2-bit global prediction
• Compare total cycles of 2-bit global prediction with that of always-taken and always-not-taken
• If you implement always-taken
• Compare total cycles of always-taken with that of always-not-taken
Submission
• Implementation fileformat
• .zipfilename:Lab4-2_{team_num}_{student1_id}_{student2_id}.zip
• Contentsofthezipfile(only*.v):
• cpu.v
• …
• Do notincludetop.v,InstMemory.v,DataMemory,andRegisterFile.v
• Report fileformat
• Lab4-2_{team_num}_{student1_id}_{student2_id}.pdf
Questions?
FAQ
• Assuming that such a situation rarely occurs in the lab, you can implement what you learned in class.
• It doesn’t matter much about the problems that cause conflict. Even if a conflict occurs, you can update it with a new target.
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FAQ
◼You don’t need to match the exact cycle of the answer.txt o It could be different following your branch prediction method o Given cycle is result of 5 stage pipeline cpu in “Ripse”
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