Description

함형규
hhk971@postech.ac.kr
Contents
n CPU structure Modularization Magic memory TSC CPU Assignment
n Tips Q&A
CPU Structure

CPU is an instruction processing FSM CPU consists of several components
̶ Datapath
• ALU, Register file, etc.. ̶ Control Unit
Datapath

̶ Units in the path of data
• SYSTEM BUS(deliver the memory data) ALU Register ALU SYSTEM BUS ̶ ALU, Register file, and other data-wires
Control unit

̶ Decodes instruction
̶ Then, generates control signals that control the components in the Datapath
Modularization
You must modularize the main CPU components
̶ Datapath
• alu.v
• register_file.v
̶ Contorl Unit
• contorl_unit.v Etc.
̶ Modularize other components if you need
• MUX, sign-extender, adder, etc..
Magic Memory
n It gives you memory data with a slight delay
(less than a clock cycle)
̶ In testbench code (line 38~58)
n It is NOT realistic model of the main memory
̶ Memory is much slower than CPU
̶ However, we assume there is a magic memory which is faster than CPU
TSC CPU
RISC-V CPU vs TSC CPU

̶ Has shorter instructions, smaller registers, and fewer instruction types!
• A simple ISA
̶ More details in TSC_manual.pdf
Assignment
Implement a single-cycle TSC CPU
̶ Your submission must include
• cpu.v
• alu.v
• register_file.v (with 4 registers)
• contorl_unit.v
̶ Your implementation of the CPU should process instruction in each clock cycle
̶ Instructions
• Implement all instructions in opcodes.v
• You don’t need to implement instructions that not containing in opcodes.v (e.g : HLT, BNI, etc..)

Tips
CPU module ports
output readM “read” signal to memory
output writeM “write” signal to memory
output [`WORD_SIZE-1:0] address target memory address
inout [`WORD_SIZE-1:0] data data for reading or writing (can be used as both input and output)
input ackOutput signal from memory (“data is written”)
input inputReady signal from memory (“data is ready for reading”)
input reset_n reset your CPU (registers, PC, etc..)
input clk clock signal
Tips (cont’d)
n About inout port
̶ Can be used as both input and output port
̶ Set wire value ‘z’ (high impedance) if you are using it as input
• You could get the input value only if it’s ‘z’ value ̶ Google for more details
Tips (cont’d)
n Negedge clk
̶ You might need 2 events in one clock cycle
• For example, CPU fetches instruction and need one more memory data fetch for load store instruction
̶ You can use both @(posedge clk) and @(negedge clk) ̶ Do not use Delay

Report Tips
Clearly distinguish between design and implementation
̶ Design
Describe how did you divide submodules and the role of the modules
̶ Implementation
Explain how did you implement each submodule
Please do not just copy your Verilog code
Q&A