Description

Clock Design Methodology
In this lab, you will learn how to use the Xilinx ISE program to design and test various clock waveforms
Introduction
For this lab, you will use the Xilinx ISE software to design and test various clock waveforms on a digital system. The Lab will go through the basic concept behind clocking a system and the techniques to generate them from a system clock,
This lab will be based on simulation only; no FPGA use will be involved. you are going to implement your design in Verilog HDL. At the end of the lab, you are expected to present a design project with source code and test bench, and the design will be focusing on comparing the different waveforms generated by your design.
Overview
The modules to design will take the system clock and a reset signal as the input and output the derived clock. There will be multiple modules in the design with one top module instantiating each of the designs for direct comparison. The top module and submodule are outlined below:
clock_gen.v Description
Divide by 2^n Clock The submodule exploring clock division by power of 2
Even Division Clock The submodule exploring even clock division
Odd Division Clock The submodule exploring odd clock division
Glitchy counter The submodule exploring pulse/strobe/flag
Background
Clocking in digital systems allows high testability. Designers can run through waveform simulation or on physical devices by stepping one clock signal and check for expected behavior. Clocks are especially important with the popularity of synchronous data transmission, allowing signals to be communicated between devices. Quick examples are serial communication links such as SPI, I2C, RS232, UART, USB, PCIe, Ethernet, etc. Additionally, clocks are often used as the basis of timer systems used in numerous embedded devices such as traffic light, monitor screens, digital stopwatches, phones, etc.
The lab will focus on creating clocks and pulses of different frequency and duty cycles.
Modules to be explored:
1. Divide by power of 2 clocks
2. Even division clock using counters
3. Odd division clock using counters
4. Single-pulse strobe
0. Counters: Introduction
In the last lab, you learned the FPGA design workflow with a combinational logic design. Now we move to the sequential circuits. In this part, you will design and perform simulations, and explain the real implementations, of several small projects revolving around counters.
4 bit counter Schematic

With the knowledge you acquired from M51A, you should be able to easily recreate the above schematic for a 4-bit counter through the use of K-maps. Xilinx ISE does provide an interface for schematics creation, however, schematic-based design methods are no longer in use in the real world. Our job here is to translate the schematics into Verilog code.
4 bit counter: Verilog Implementation

Since we are translating the schematics, each gate should be mapped to an operator, and each flip-flop should be mapped to one line in the edge-sensitive always block. Remember to use the non-blocking assignment <= in edge-sensitive always blocks. When synthesized, the code will produce the same circuit as the schematic. Create a new module with an input clk, rst, and output a. Write a testbench for the above code snippet and test it in simulation. Set the input clock frequency to 100 Mhz in the testbench.
1. Clock Divider by Power of 2s:
Verify that the 4-bit counter works. Open up the waveform window and analyze the counter signals. You will notice that the least significant bit (LSB) of the counter is a direct division of 2. The 1st bit is 4 times as slow. The 2nd bit is 8 times as slow. From this you can see that a clock divider can be obtained by extracting the proper bit from the counter.
Design Task: Assign 4 1-bit wires to each of the bits from the 4-bit counter (1)
2. Even Division Clock Using Counters:
In continuation of the 4-bit counter design, generate the divide by 32 clocks by flipping the output clock on every counter overflow. (2)
In this design, the counter counts from 0 to 15 in decimal. On the 16th(0th) edge the output will flip. The total period of 1 clock pulse will be 32 positive edges or 32 times slower.
Design Task: Generate a clock that is 26 times smaller by modifying when the counter resets to 0. (3)
3. Odd Division Clock Using Counters:
Generate a 33% duty cycle clock using if statement and counters and verify the waveform.
(4)
Duplicate the design in another always block that triggers on the falling edge instead. View the two-waveform side by side. (5)
What happens if you assign a wire that takes the logical or of the two 33% clocks. (6)
Design Task: Generate a 50% duty cycle divide-by-5 clock. (7)
4. Pulse/Strobes:
Create a divide-by-100 clock with only 1% duty cycle using the counter methods previously introduced in parts 2 and 3. Create a second always block that runs on the system clock (100Mhz) and switch the output clock every time the divide-by-100 pulse is active with an if statement. Verify that the output clock is 50% duty cycle divide by 200 clock running at 500Khz. (8)
Design task: Use the master clock and a divide-by-4 strobe to generate an 8-bit counter that counts up by 3 on every positive edge of the master clock, but subtracts by 5 on every strobe. The sequence generated should be as shown below:
0→3→ 6→9→4→7→>10 -> 13→ 8 -> 11 -> 14 -> 17 -> 12 … (9)
Deliverables
Make sure you obtain all 14 waveforms for the top level module as shown below

An example output of a successful Clock Gen Module waveform is shown above. The signals are ordered from top to bottom as the following
1. Divide by 2 clock (task 1) 2. Divide by 4 clock (task 1)
3. Divide by 8 clock (task 1)
4. Divide by 16 clock (task 1) 5. Divide by 32 clock (task 2)
6. Divide by 26 clock (task 3)
7. Divide by 3 clock (task 6)
8. 33% duty clock (task 4)
9. 33% duty clock with negative edge triggered (task 5)
10. Divide by 5 clock (task 7)
11. 500 kHz clock (task 8)
12. Glitchy counter (task 9)
13. Input clock
14. Reset Signal
The project consists of verification tasks and design tasks indexed by 1-9. You need to implement all the 9 tasks and add waveforms and a brief explanation for all tasks in your report. The final Verilog code that you submit should be the clock_gen module as explained above (the inputs and outputs for the module clock_gen are listed below in the sub-section ‘Interface’). When you finish, the following should be submitted for this lab:
1. Verilog source code for the “clock_gen” module. The file should be named exactly as “clock_gen.v” and the module and port names should exactly match names defined in the last page. Also, note that this code should be completely synthesizable. There is no restriction on the naming of the submodules but make sure to place all the submodules in the clock_gen.v file. An example is outlined on the last page.
2. Verilog testbench you used to evaluate your design. Note that your testbench is graded based on the correctness of the waveforms generated in your report. Please name the file “testbench_UID.v” where UID is your UCLA ID.
3. Lab Report should be consisting of explanations about your module and testbench design. Explain ideas you used to implement different blocks. Also, explain how you test your design. Please document the waveforms for all verify tasks and design tasks. Generate a waveform for the final Clock Generator showing all the 9 ports. Please name your report “UID.pdf” where UID is your UCLA ID.
4. Video Demo: a 10 minute video showing your screen and focusing on the final clock_gen.v module and explaining the concepts utilized from previous sections. Interface
module clock_gen( input clk_in, input rst, output clk_div_2, output clk_div_4, output clk_div_8, output clk_div_16, output clk_div_32, output clk_div_26, output clk_div_3, output clk_pos, output clk_neg, output clk_div_5, output clk_div,
output [7:0] toggle_counter
);
endmodule
Example of clock_gen.v
This is an example of the modules and sub-modules you can use in clock_gen.v. As long as the interface of clock_gen is as specified, you are free to define the internals/sub-modules differently.
module clock_gen( input clk_in, input rst, output clk_div_2, output clk_div_4, output clk_div_8, output clk_div_16, output clk_div_32, output clk_div_26, output clk_div_3, output clk_pos, output clk_neg, output clk_div_5, output clk_div,
output [7:0] toggle_counter );
clock_div_two task1(
.clk_in (clk_in),
.rst (rst),
.clk_div_2(clk_div_2),
.clk_div_4(clk_div_4),
.clk_div_8(clk_div_8),
.clk_div_16(clk_div_16)
);
clock_div_thirty_two task2 (
.clk_in(clk_in),
.rst(rst),
.clk_div_32(clk_div_32)
);
clock_div_twenty_six task3(
.clk_in (clk_in),
.rst (rst),
.clk_div_26 (clk_div_26)
); clock_div_three task456( .clk_in(clk_in),
.rst(rst),
.clk_div_3(clk_div_3),
.clk_pos(clk_pos),
.clk_neg(clk_neg)
);
clock_div_five task7(
.clk_in (clk_in),
.rst (rst),
.clk_div_5 (clk_div_5)
);
clock_pulse task8(
.clk_in(clk_in),
.rst(rst),
.clk_div(clk_div)
);
clock_strobe task9(
.clk_in (clk_in),
.rst (rst),
.toggle_counter (toggle_counter)
); endmodule
// task 1
module clock_div_two(clk_in, rst, clk_div_2, clk_div_4, clk_div_8, clk_div_16); input clk_in, rst;
output clk_div_2, clk_div_4, clk_div_8, clk_div_16; endmodule
// task 2
module clock_div_thirty_two(clk_in, rst, clk_div_32); input clk_in, rst; output reg clk_div_32; endmodule
// task 3
module clock_div_twenty_six(clk_in, rst, clk_div_26); input clk_in, rst; output reg clk_div_26; endmodule
// task 4, 5, 6
module clock_div_three(clk_in, rst, clk_div_3, clk_pos, clk_neg); input clk_in, rst; output clk_div_3; output reg clk_pos, clk_neg; endmodule
// task 7
module clock_div_five(clk_in, rst, clk_div_5); input clk_in, rst; output clk_div_5; endmodule
// task 8
module clock_pulse(clk_in, rst, clk_div); input clk_in, rst; output reg clk_div; endmodule
// task 9
module clock_strobe(clk_in, rst, toggle_counter); input clk_in, rst; output reg [7:0] toggle_counter; endmodule