Description

Lab Location: EA-Z04

Purpose: In this lab you will use the digital design engineering tools (System Verilog HDL, Xilinx Vivado and FPGA, Digilent BASYS3 development board) to modify the single-cycle MIPS processor. You will expand the instruction set of the “MIPS-lite” processor by adding new instructions to it. To do this, you must first determine the RTL expressions of the new instructions then modify the datapath and control unit of the MIPS. To implement the new instructions will require you to modify some System Verilog modules in the HDL model of the processor. To test and prove correctness, you will first simulate the microarchitecture, then synthesize it and demonstrate on the BASYS3 board.

Summary

Part 2 (50 points): Simulation of the MIPS-lite processor (25%) and Implementation and Testing of new instructions (25%).

We use MOSS testing only for code submissions. So, you are not supposed to submit the whole preliminary report online. You will ONLY submit the code online.

No late submission will be accepted.

At the conclusion of the demo for getting your grade, you will upload your lab (only lab) program work to the Unilica Assignment, for similarity testing by MOSS. See Part 3 below for details.

[REMINDER!] In this lab and the next one, we assume SystemVerilog knowledge, as well as the ability to use tools such as Xilinx Vivado and Digilent BASYS3 Board, since you all took CS223 – Digital Design. If you are not familiar with these, please get used to them as soon as possible.

Part 1. Preliminary Work / Preliminary Design Report (50 points)

Be sure to make a copy of the report, to use during the lab. Your preliminary design report should contain the following 7 items, one per page:

a) You have to provide a neat presentation prepared by Word or a word processor with similar output quality such as Latex as you were asked in Lab 1. At the top of the paper on left provide the following information and staple all papers. In this part provide the program listings with proper identification (please make sure that this info is there for proper grading of your work, otherwise some points will be taken off).
CS224
Your Full Name/Bilkent ID

c) [5 points] Register Transfer Level (RTL) expressions for each of the new instructions that you are adding (see list below for your section), including the fetch and the updating of the PC.
d) [5 points] Make any additions or changes to the datapath which are needed in order to make the RTLs for the instructions possible. The base datapath should be in black, with changes marked in red and other colors (one color per new instruction). Do NOT use yellow.
e) [5 points] Make a new row in the main control table for each new instruction being added, and if necessary add new columns for any new control signals that are needed (input or output). Be sure to completely fill in the table—all values must be specified. If any changes are needed in the ALU decoder table, give this table in its new form (with new rows, columns, etc). The base table should be in black, with changes marked in red and other colors. {Note: if you need new ALUOp bits to encode new values, you should also give a new version of Table 7.1, showing the new encodings}
f) [10 points] Write a test program in MIPS assembly language, that will show whether the new instructions are working or not, and that will confirm that all existing old instructions still continue to work. Don’t use any pseudo-instructions; use only real MIPS instructions that will be recognized by the new control unit.
g) [20 points] Write a list of the System Verilog modules that will need changes in order to make these new instructions part of the single-cycle MIPS processor’s instruction set. For each module in the list, determine the new System Verilog model that will be needed in order for the instructions to be added. Give the System Verilog code for each module that needs to be changed.

Table of instructions to implement– by section

Table of Instructions to Implement (by section)
Section MIPS instructions Section MIPS instructions
Sec 1 Base: Original10 New: “ble”, “sw+” Sec 4 Base: Original10 New: “jm”, “blt”
Sec 2 Base: Original10 New: “nop”, “subi” Sec 5 Base: Original10 New: “jalm”, lui
Sec 3 Base: Original10 New: “bge”, “swapRM” Sec 6 Base: Original10 New: jalr, “bgt”

(The Original10 instructions in “MIPS-lite” are add, sub, and, or, slt, lw, sw, beq, addi and j. Definitions of the new instructions are given below.)

Instructions in quotes (e.g.”sw+”) are not defined in the MIPS instruction set. They don’t exist in any MIPS documentation, they are completely new to MIPS. You will create them, according to the definitions below, then implement them.

nop: This I-type instruction does nothing, changes no values, takes one clock cycle. Except for the opcode (which you need to assign a code to), the I-type instruction field values are irrelevant. Example: nop {Note: an R-type nop exists in real MIPS, it is sll $0, $0, 0. But the nop here is different, so it is “nop” !}

subi: This I-type instruction subtracts, using a sign-extended immediate value. subi $t2, $t7, 4

jm: This I-type instruction is a jump, to the address stored in the memory location indicated in the standard way. Example: jm 40($s3)

jalm: This I-type instruction is a jump, to the address stored in the memory location indicated in the standard way. But it also puts the return address into the register specified. Example: jalm $t5, 40($s3)

bge, bgt, ble, blt: These I-type instructions do what you would expect—branch to the target address, if the condition is met. Otherwise, the branch is not taken. Example: bge $t2, $t7, TopLoop

swapRM: This I-type instruction exchanges the data in two locations: the exchange is between a register value and a memory value (addressed in the standard way). Example: swapRM $v0, 1004($sp)

sw+: [a similar version done in class/quiz] This I-type instruction does the normal store, as expected, plus an increment (by 4, since it is a word transfer) of the base address in RF[rs]. {Note: these kind of auto-increment/decrement instructions are useful when moving through an array of data words.}

Part 2: Simulation and Implementation

Simulation of the MIPS-lite processor (25%)
a) Complete the System Verilog model of single-cycle MIPS by designing a 32-bit ALU module (one is partly specified already in “Complete MIPS model.txt”) and save this ALU module by itself in a new file with a meaningful name. Make this file the basis of a new Xilinx Vivado project. In simulation, check its syntax, and then simulate this ALU, using a testbench that you will write. When you are sure that the 32bit ALU is working correctly in simulation, you can now use it in the MIPS-lite datapath. When you have integrated your working 32-bit ALU into the “Complete MIPS model.txt” file, you are ready to simulate the MIPS-lite single-cycle processor in Xilinx Vivado.
b) Make a New Project, giving it a meaningful name, for your single-cycle MIPS-lite. Do Add Source for the System Verilog modules given in “Complete MIPS model.txt” (modified with your working ALU), and Save everything.
c) Study the small test program loaded into instruction memory (in the imem module) that you disassembled in part b) of your Preliminary Design Report. What is the program attempting to do?
d) Now make a System Verilog testbench file and using Xilinx Vivado, simulate your MIPS-lite processor executing the test program. Study the results given in the simulation window. Find each instruction, and understand its values. Why is writedata undefined for some of the early instructions in the program?
e) Now modify the simulation, in order to show more information. Make changes to the System Verilog modules as needed so that the 32-bit values of PC and the Instruction are made to be outputs of the toplevel module. Then modify the testbench file, so that they are displayed in the simulation.
Now save the System Verilog code of the testbench module used for your simulation in part f), plus the top-level module file that you used for part f), in their final form. Put these 2 modules together in a text file named StudentID_StudentFirstName_StudentLastName_SecNo_LabNo_LAB.txt. It should contain all the System Verilog codes from these 2 modules, copy-pasted together in one .txt file, but no other modules. In Part 3 but not now, you will upload your file to the Unilica Assignment for your section, for similarity checking with MOSS. Each person is only allowed to upload 1 submission the Unilica Assignment, and now is not the time.

Adding New Instructions: Implementation and Testing (25%)
g) Implement the modified processor by making the necessary changes to the System Verilog modules inyour Preliminary Design Report, part g). Integrate these all together into a new System Verilog model for the MIPS single-cycle processor that does the Original10 instructions plus the new instructions required for your section.

You should also consider the following: to slow down the execution to an observable rate, the clock signal should be hand-pushed, to be under user control. One clock pulse per push and release means one instruction is fetched-decoded-executed. Similarly the reset signal should be under hand-pushed user control. So these inputs need to come from push buttons, and to be debounced and synchronized. The memwrite output (along with any other control signals that you want to bring out for viewing) can go to a LED, but the low-order bits of writedata (which is RF[rt]) and of dataaddr (which is the ALU result) should go to the 7-segment display, in order to be viewed in a human-understandable way. [Consider why it isn’t necessary to see all 32 bits of these busses, just the low-order bits are enough.]

h) In view of the above, create a new top-level System Verilog module, to model the system that containsan instantiation of the MIPS computer (in module top), as well as 2 instantiations of pulse_controller, and 1 instantiation of display_controller. Your system should include some hand-pushed signals coming from push buttons, and some anode and cathode outputs going to the 7-segment display unit on the BASYS3 board and memwrite (and possibly other outputs) going to a LED..

i) Make the constraint file that maps the inputs and outputs of your top-level System Verilog model to theinputs (100 Mhz clock and pushbutton switches) and outputs (AN and CA signals to the 7-segment display, and memwrite (plus others?) going to a LED) of the BASYS3 board and its FPGA.

Part 3. Submit your code for MOSS similarity testing
In Part 2, you created a new top-level module for your overall system, and modified several System Verilog modules for parts of the single-cycle MIPS that needed to change in order to implement the new instructions. Now it is time to combine all the new and modified System Verilog codes into a file called instructions. Now it is time to combine all the new and modified System Verilog codes into a file called StudentID_FirstName_LastName_SecNo_LAB_LabNo.txt. This is the file you started in Part 2 (after f, your simulation demo). Now add to it all the Verilog modules whose code is new or modified for j, the implementation demo. DO NOT include any unmodified System Verilog modules, only those whose code you changed or created. When you have done this, StudentID_FirstName_LastName_SecNo_LAB_LabNo.txt will contain 2 System Verilog modules from Part 2 (simulation), and several more System Verilog modules from Part 2 (implementation).

After demonstrating your working (or partially working) codes to the grader, you should immediately submit your MIPS codes for similarity testing to the Unilica > Assignment specific for your section. You will upload one file, named
StudentID_StudentFirstName_StudentLastName_SecNo_LabNo_PRELIM.txt
We use MOSS testing only for code submissions. So, you are not supposed to submit the whole preliminary report online. You will ONLY submit the code online.

Part 4. Cleanup
1. After saving any files that you might want to have in the future to your own storage device, erase all the files you created from the computer in the lab.
2. When applicable put back all the hardware, boards, wires, tools, etc where they came from.
3. Clean up your lab desk, to leave it completely clean and ready for the next group who will come.

Part 5. Lab Policies
1. You can do the lab only in your section. Missing your section time and doing in another day is not allowed.
4. You must be in lab, working on the lab, from the time lab starts until your work is finished and you leave.
5. No cell phone usage during lab.
6. Internet usage is permitted only to lab-related technical sites.
7. For labs that involve hardware for design you will always use the same board provided to you by the lab engineer.
1