Description

Description of design:
You need to design a data compression circuit using run-length encoding. It replaces continuously repeated occurrences of a byte with a repeat count and the byte value. The circuit receives a fresh byte at every positive transition of an externally supplied clock. We shall use the ‘ESC’ character (code = 1BH) to signal the use of a repeat count. Therefore, if the ‘ESC’ character itself appears in the input stream, it has to be handled in a special way. The output is one byte wide and every data byte being output is signalled by a rising transition on a DataValid line.
● If any character ‘c’ repeats ‘n’ times in the input stream such that 2<n<6 then we output the three-byte sequence “ESC n c”.
● If ‘n’ number of ‘ESC’ characters arrive contiguously in the input stream, we output the 3-byte sequence “ESC n ESC”, where n can be from 0<n<7. Otherwise, we just output the received characters without any change.
● Notice that in both of the above cases since the output of your circuit is only 1 byte wide, it cannot output all the 3 bytes at once. Only 1 byte is output per clock cycle and whenever a byte is being output, the Data Valid output line must go from low to high.
● If the repeat count is more than 5, we handle the first 5 characters as above and treat the 6th occurrence onwards as if a new character has been received.
● This circuit reads from an input file and sends the output to an output file. The reading and writing operations are done in the test bench itself. (Hint: Look at the video of creating a fully automated test bench to know how to read something from a file into the test bench and write something from test bench into another file)
● For the purpose of testing make your own input file (the input file should be named as input.txt) with the following constraints.
■ The data should be present in binary ASCII format (Make use of the ASCII table that will be shared with you).
■ Only small letter alphabets can be used. Besides ‘ESC’ and ‘SPACE’, no other
special character is permitted.
■ There should be only one character per line in the file. (That is every line will have only 8 binary bits).
■ The file should have exactly 64 bytes. (i.e. exactly 644 characters).
● The testbench will read the output from your circuit and print it into an output file (should be named output.txt). It will print only one character (8 bits) per line.
Things required in Submission:
1. All VHDL files of top-level and sub-components. (.vhd or .vhdl files)
2. Test bench file for the top-level module.
3. Screenshot of Waveform.
4. A document should be submitted which should contain:
a. Block diagram of your entire design including your RLE encoder, file reader and file writer (both file reading and writing operations can be done in the test bench itself).
b. A detailed explanation of the design of each and every module.
Submission rules:
2. Create a folder named lab6 (all small letters and no spaces).
3. Inside the folder, put all the .vhd or .vhdl files of both top-level entity and sub-components. Also in the same folder put the related waveform screenshots and pdf report.
4. Finally, before you submit the lab6 folder on moodle you will be zipping it. The zip file should have your id number as the name. For eg: if your id is 184070026 then your zip file will be 184070026.zip.