Description

Minsu Gong
gongms@postech.ac.kr
Contact the TAs at csed311-ta@postech.ac.kr
Contents
• Assignments
• Single-Cycle CPU (RV32I)
• Ripes simulator
• How to run C program on Ripes & Verilog RTL (Non-mandatory)

• Use Verilator
• Implement a single-cycle RISC-V CPU (RV32I)
• Single-cycle CPU
• Datapath
• ALU
• Register file
• Control unit
• Generate the control signals used in the datapath
• Your implementation of the CPU should process one instruction in a cycle
• Skeleton code
• top.v – Top module (Do not touch)
• opcodes.v – Opcodes of instructions you must implement
• Other modules (add more if you need)
• cpu.v, instruction_memory.v, data_memory.v, register_file.v
• Testbench
• Simulation code
• tb_top.cpp
• Instruction codes for Verilog RTL (.txt)
• basic_ripes.txt, non-controlflow_mem.txt, loop_mem.txt
• Assembly codes for Ripes (.asm) (will explain later)
• basic_ripes.asm, non-controlflow_mem.asm, loop_mem.asm • Makefile
• RV32I instructions you should implement

• We are going to use the ECALL (environment call) instruction to halt the machine at the end of a program
• Simulation ending condition
• If instruction == ECALL
• If GPR[x17] == 10
• Set is_halted = 1 (Testbench will stop simulation when is_halted is 1)
• Else
• Consider ECALL as NOP
• Example of instructions exiting the program

• For other instructions, refer to the RV32I manual
• References:
• See RISC-V specification (Vol. 1) provided for the lab
• https://github.com/riscv/riscv-isa-manual/releases/tag/Ratified-IMAFDQC
• https://msyksphinz-self.github.io/riscv-isadoc/html/rvi.html

Modularization
• Modularize the main CPU structure (strongly recommended)
• Datapath
• ALU
• Register file • Control Unit
• Etc.
• MUX, adder, ..
• Keep one module in one Verilog file (Verilator issue)
• Match file name with module name (Verilator issue)
Magic Memory
• In instruction_memory.v, data_memory.v
• It is NOT a realistic model of the main memory
• In our lab, memory works like a register file, except that the memory is byte-addressable and accessed with memory address instead of register ID
• Real memory devices are much slower than CPUs
• However, we assume there is a magic memory with very low latency for simplicity
Initialize instruction memory
The number of instructions < MEM_DEPTH

Evaluation Criteria (Source code)
• Single-Cycle CPU
• The score will be calculated based on the final register values (x1-x31) of the Verilog RTL after testbenches for evaluation are executed (i.e., how many registers have the correct values)
• Testbench will print final register values
• You can check correct register values by running .asm file with Ripes
• You are encouraged to run your own program on your Verilog RTL model
Evaluation Criteria (Report)
• You can write report in Korean or English
• Report should include (1) introduction, (2) design, (3) implementation, (4) discussion, and (5) conclusion
• Key points:
• Single-cycle CPU design and implementation
• Description of whether each module(RF, memory, PC, control unit, ..) is clock synchronous or asynchronous
• Description of each stage in single-cycle CPU
Assignment Submission
• Submit your assignment to PLMS with filename:
• Lab2_{TeamID}_{StudentID1}_{StudentID2}.pdf
• PDF file of your report
• Lab2_{TeamID}_{StudentID1}_{StudentID2}.zip
• Zip file of your source code (without testbench)
• One directory including all codes when unzipped

• Ripes is a visual computer architecture simulator and assembly code editor built for the RISC-V instruction set architecture
• Ripes can help you debug code

• How to install?
• https://github.com/mortbopet/Ripes/releases
• Install the lastest version

• Follow the instruction in the link above
• Web version is also available
• https://ripes.me/
• But you can’t load a program with web version.
• Still, you can copy and paste your code to editor

Processor configuration

Loading a program

Loading a program
• For web version,
• You can’t load a program with web version.
• Still, you can copy and paste your code to editor

Running the program

As you can see, assembly code uses pseudo-instructions and register aliases.
See “RISC-V Assembly Programmer’s Handbook” Chapter of RISC-V manual.
x10 issue

x10 issue

In Ripes Simulator, x10 holds the system call instruction’s index when it is called.
You don’t need to implement this on your CPU.

• How to install?
• Use Docker (MacOS/Windows/Linux Support)
• For Windows users,
• Use CSE Education Slurm Cluster to use Docker
• You can request the account of CSE Education Slurm Cluster at the below link
• https://postechackr.sharepoint.com/sites/cse/SitePages/CSE-Cluster-
Howto.aspx?csf=1&e=qwAkG9&cid=dfb4c189-2455-4381-a8c1-2489054f57bb • Or, use WSL to run docker on your computer
• Get docker image
• $ docker pull acplpostech/acpl_ubuntu_18.04_riscv:latest
• Start docker
• $ docker run -v ~:/mnt -it –rm acplpostech/acpl_ubuntu_18.04_riscv:latest /bin/bash
• Risc-V Assembly Code Generate (Use /RISCV_Crosscompile/script.sh)
• $ cd /RISCV_Crosscompile
• $ ./script.sh file_name
C Code (example.c) Assembly Code

• Risc-V Assembly Code Generate (Use /RISCV_Crosscompile/script.sh)
• Output file
• /RISCV_Crosscompile/{file_name}_ripes.asm -> for Ripes input
• $ mv /RISCV_Crosscompile/{file_name}_ripes.asm /mnt
• $ exit #exit docker
• Now you can find {file_name}_ripes.asm in home directory

Caution
• Since we model RV32I without the “M” extension for multiply/divide, you can’t use multiplication on the c code
• You can still multiply or divide by a power of 2 using shift left or right operations
• You will need to implement some additional instructions that are commonly emitted by the compiler
Assignments (Optional)
• Implement LUI and AUIPC if you want

1. Make new program with cross-compiler output file ({file_name}_ripes.asm)

2. Move the <main> function to the top (because default PC is 0x0 in Ripes)

3. Replace ‘jalr zero, 0(ra)’ at the end of <main> with ‘li a7, 10’ & ‘ecall’ (exit inst.)

4. For every function call, replace ‘auipc ra, 0x0’ & ‘jalr ra, 0(ra)’ with ‘jal ra, <add_func>’ (target function)

5. For every function return, replace ‘jalr zero, 0(ra)’ with ‘jr ra’ (return)

6. Now you can simulate the source code in Ripes.

7. Use parser.sh in Docker to extract HEX instruction code from Ripes disassembled instruction code

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