Description

Jinhoon Bae
bae00003@postech.ac.kr
Contact the TAs at csed311-ta@postech.ac.kr
Contents
◼ Objectives
◼ Multi-cycle CPU
◼ Assignment
Objectives
◼ Understand why a multi-cycle CPU is better than single-cycle implementation
◼ Design and implement a multi-cycle CPU, which has its own datapath and control unit
Why Multi-Cycle CPU?
◼ Problem on single-cycle CPU: underutilization of resources (ALU, memory, register file, etc.)
◼ Solution: use higher clock frequency and allocate a different number of cycles for each instruction type

Multi-Cycle CPU (Finite State Machine)

Multi-Cycle CPU (Microcode Controller)

Single-Cycle CPU (Datapath w/o Resource reuse)

Multi-Cycle CPU (Datapath w/ Resource Reuse)

Multi-Cycle CPU
◼Details for multi-cycle CPU are given in the lecture note and textbook
̶ Appendix C can also be helpful
̶ Link: https://www.elsevier.com/books-and-journals/book-companion/9780128203316
Assignment
◼ Use Verilator
◼ Implement a multi-cycle RISC-V CPU (RV32I)
̶ Multi-cycle CPU
• Datapath
− ALU
− Register file
• Control unit
− Microcode controller
− Generate the control signals used in the datapath
̶ You can use FSM with either 1 cycle or more cycles for each stage
Assignment
• Skeleton code updated
• Top.v, cpu.v, RegisterFile.v, and memory.v are updated
• You can take other modules (e.g., ALU) from your single-cycle CPU to implement the multicycle CPU • Other modules (add more or change if you need)
• Testbench
• Simulation code
• tb_top.cpp
• Instruction codes for Verilog RTL (.txt)
• basic_ripes.txt, non-controlflow_mem.txt, loop_mem.txt, ifelse_mem.txt, recursive_mem.txt
• Assembly codes for Ripes (.asm) (will explain later)
• basic_ripes.asm, non-controlflow_mem.asm, loop_mem.asm, ifelse_mem.asm, recursive _mem.asm
• Makefile
Assignment (cont’d)
◼Implement the same instructions required in the single-cycle CPU

Modularization
◼ Modularize the main CPU structure (strongly recommended)
̶ Datapath
• ALU
• Register file ̶ Control unit
• Microcode controller ̶ Etc.
• MUX, …
Evaluation Criteria
◼Source code
̶ The score will be calculated based on the final register values (x1-x31) of the Verilog RTL after test cases for evaluation are executed (same as single-cycle CPU)
• You can check the correct register values with single-cycle Ripes simulation (Ripes doesn’t support multi-cycle simulation) ̶ Implementation guidelines
• Your control unit should be a well-implemented state machine
− Each state should generate its control signals
• All storage units (registers, PC, etc.) must be updated only at the clock’s positive edges
• Your code should have resource reuse, which affects your control unit design
− E.g.) Combining “PC + 1” logic with the ALU
• If you don’t follow guidelines, you will get penalty
Evaluation Criteria (cont’d)
◼Report
̶ The report should include (1) introduction, (2) design, (3) implementation, (4) discussion, and (5) conclusion sections
̶ Attach screenshots of your microcode controller, control unit code in the report ̶ Key points:
• Difference between single-cycle CPU and multi-cycle CPU
• Why multi-cycle CPU is better?
• Multi-cycle CPU design and implementation
• Description of whether each module (RF, memory, PC, control unit, ..) is clock synchronous or asynchronous
• Microcode controller state design
• Resource reuse design and implementation
• Number of cycles took it took to run basic_ripes, and loop_ripes examples
Submission
◼ Submit your report and source code on PLMS with filename:
̶ Lab3_{TeamID}_{StudentID1}_{StudentID2}.pdf Zip file contents
• PDF file of your report (note there is no folder):
̶ Lab3_{TeamID}_{StudentID1}_{StudentID2}.zip
• Zip file of your source code (without testbench)
• Do not create a folder within the zip file
◼ There can be penalties for submissions that do not adhere to the guidelines
◼Submission
̶ Evaluation will be done with all instructions (both control-flow and non-control-flow instructions)

Questions?