Description

Electrical and Computer Engineering Department
Digital Logic Design, ECE 367, 894, Fall 1400
Computer Assignment 1
Basic Switch and Gate Structures in Verilog
Week 3-4

Name:

1. Show switch level structure of a 2-input NAND gate and a NOT gate using nMOS and pMOS structures that have #(3,5,7) and #(4,7,9) delay values respectively.
a. Show the schematic diagram of the circuits.
b. Manually, hand simulate the circuits and, in a timing-diagram, show the two delay values To1 and To0 for each gate.
c. Write switch-level description of the NAND and NOT gates in SystemVerilog.
d. Write a testbench for the above circuits and using test data from the testbench apply inputs to cause the circuits’ worst-case delays. Make sure the changes on inputs are far enough apart to put the circuits into a steady-state before the next input change.
e. Compare your hand-simulation and the SystemVerilog simulation and explain the differences, if any.

2. Show switch level structure of a 2-input NAND gate with a three-state control input and a NOT gate with such control. For the NAND gate, if the three-state control is 1, the output is the NAND of the two inputs, and if it is 0, the output is at Z. The three-state NOT gate works in a similar fashion. See the circuit in Homework 1.
a. Show the schematic diagram of the circuits.
b. Manually, hand simulate the circuits and, in a timing-diagram, show the three delay values To1, To0, and ToZ for each gate.
c. Write switch-level descriptions of the three-state NAND and NOT gates in SystemVerilog.
d. Write a testbench for the above circuits and using test data from the testbench apply inputs to cause the circuits’ worst-case delays. Make sure the changes on inputs are far enough apart to put the circuits into a steady-state before the next input change.
e. Compare your hand-simulation and the SystemVerilog simulation and explain the differences, if any.

3. Using gates of Part 1 develop a circuit for implementing w = d’ . c’ + d . (a.b)’. The elements of this circuit are gates of Part 1.
a. Show the schematic diagram of the circuit.
b. Manually, hand simulate the circuit and, in a timing-diagram, show the delay values To1, and To0 for w. Use worst-case delay values calculated in Part 1.
c. Write a testbench for the above circuit and using test data from the testbench apply inputs to cause the circuits’ worst-case delays. Make sure the changes on inputs are far enough apart to put the circuits into a steady-state before the next input change.
d. Compare your hand-simulation and the SystemVerilog simulation and explain the differences, if any.

4. Using gates of Part 2 develop a circuit for implementing w = d’ . c’ + d . (a.b)’. The elements of this circuit are gates of Part 2.
a. Show the schematic diagram of the circuit.
b. Manually, hand simulate the circuit and, in a timing-diagram, show the delay values To1, and To0 for w. Use worst-case delay values calculated in Part 1.
c. Write a testbench for the above circuit and using test data from the testbench apply inputs to cause the circuits’ worst-case delays. Make sure the changes on inputs are far enough apart to put the circuits into a steady-state before the next input change.
d. Compare your hand-simulation and the SystemVerilog simulation and explain the differences, if any.

5. Show switch level structure of a CMOS Complex Gate for implementing w = d’ . c’ + d . (a.b)’. Use nMOS and pMOS structures that have #(3,5,7) and #(4,7,9) delay values respectively.
a. Show transistor level schematic diagram of the circuit.
b. Manually, hand simulate the circuit and, in a timing-diagram, show the delay values To1, and To0 for w.
c. Write a testbench for the above circuit and using test data from the testbench apply inputs to cause the circuits’ worst-case delays. Make sure the changes on inputs are far enough apart to put the circuits into a steady-state before the next input change.
d. Compare your hand-simulation and the SystemVerilog simulation and explain the differences, if any.

6. Compare circuits of Part 3, 4 and 5. You are to develop a testbench and instantiate all three circuits.
a. Show block diagram of your testbench in which the three circuits are instantiated.
c. Compare the circuits in terms of timing, number of transistors, and power consumption. Explain how you are estimating power consumptions of the three structures.

Deliverables:

Generate a report that includes all the items below:

Make a PDF file of your report and name it with the format shown below:
FirstinitialLastnameStudentnumber-CAnn-ECEmmm

Where nn is a two-digit number for the Computer Assignment, mmm is the three-digit course number under which you are registered, and hopefully you know the rest. For the Firstinitial use only one character. For Lastname and for the multi-part last names use the part you are most identified with. Use the last five digits of your student id (exclude 8101) for the Studentnumber field of the report file name.