Description

FPGA Implementation of Simple Quality of Service (QoS) based Queuing
1 Introduction
2 Project definition
2.1 Project Summary
2.1.1 Latency Requirement
Latency precedence for the buffers is given as Buffer 1 > Buffer 2 > Buffer 3 > Buffer 4. This means that the lowest delay is desired for Buffer 1. For example, if some data are available at Buffer 1 and Buffer 2, Buffer 1 should be read first.
2.1.2 Reliability Requirement
Reliability precedence for the buffers is Buffer 4 > Buffer 3 > Buffer 2 > Buffer 1. This means that the lowest packet drop rate is desired for Buffer 4. But you should note that you should minimize the overall packet drops to achieve desired performance.
Also, once data is read from a buffer you should delete that data, and shift the remaining data by one register.
Number of transm tted packets transferred as Output Data
Buffer 2 Buffer 3 Buffer 4 Total
20 15 50 125
Number of rec eved packets from FPGA buttons
Buffer 2 Buffer 3 Buffer 4 Total
25 15 50 140
Number of dropped packets
Buffer 2 Buffer 3 Buffer 4 Total
5 0 0 15
Figure 1: Example Buffering System.
2.2 Project Requirements
To define the requirements one by one as a list:
1. You should present the buffers and the available data values inside the buffers.
2. The number of transmitted packets, the number of received packets, and the number of dropped packets should be printed. • When new data arrives via FPGA buttons, buffer contents and the corresponding numbers on the right-hand side should change.
• At every 3 seconds, a single register from one of the buffers is read and should be printed as output. Also, necessary deletion operations and number updates should be performed.
3 Final Words
This is not a last-night project. You must put an effort on it to be successful. On the other hand, do not worry. This is a straightforward project in general.
Please keep in mind that we have limited resources and we must benefit wisely so that new students can also benefit. FPGA boards are sensitive, fragile, and expensive boards. Now, they are in perfect condition. For the duration you borrowed them from us, you will be responsible for taking care of them. Once the time to give FPGA boards back is reached, you must give your borrowed FPGA back in perfect condition as well. Failing to give back to the FPGA board will result in a harsh penalty.
As you can notice also, some details regarding the project are left to you. For some parts, there are nearly infinite options. We would like to remind you that cheating is a serious issue, which will be strictly penalized. We hope that all of you will do creative and successful project demonstrations. Enjoy.
4 Deliverables
To complete the project work, you need to submit a video presentation and a final report, and attend the demonstrations. Deadlines are as follows:
4.1 Design proposal video presentation
Each group needs to prepare a design proposal presentation of their preliminary research about the term project. At this stage your solution does not need to be fully functional. However, you need to offer a solution to every requirement of the project.
Requirements for the video can be summarized as:
• A presentation needs to be prepared using PowerPoint or equivalent applications.
• Group members need to make the presentation over zoom and record it as a video.
• In the video, both presentation and presenter need to be visible.
• All group members need to contribute to the video equally.
• Video duration needs to be at most 5 minutes.
• Presentation must include the problem definition and solution proposal, including block and state diagrams.
4.2 Final report
You are going to submit a final report. In the report, you are going to explain your conceptual design or solutions to the requirements for the project. State diagrams defining your logic scheme, theoretical understanding of VGA and buttons and pictures of the working system should be included as well.
4.3 Project demonstrations
Demonstrations will be held in the laboratory after final exams. Each group member needs to be able to explain the design, present the system on the FPGA board and answer the assistants’ questions.