Description

Lab 5: Keyboard and Audio Modules
Prof. Chun-Yi Lee
Agenda
Lab 5 Outline
Lab 5 Rules
Lab 5 Submission Requirements
Source codes and testbenches
Please follow the templates EXACTLY
We will test your codes by TAs’ testbenches
Lab 5 report
Please submit your report in a single PDF file
Please draw the block diagrams and state transition diagrams of your designs
Please explain your designs in detail
Please list the contributions of each team member clearly
Please explain how you test your design
What you have learned from Lab 5
Agenda
Basic Questions
Basic FPGA Demonstration 1
Agenda
Advanced Questions
Verilog Advanced Question 1
Sliding Window sequence detector (mealy machine)
Detect the sequence 1100(10)+01 (in regular expression)
The pattern 10 in the middle have to appear at least once and can be repeated.
For example, 11001001 is a match, 1100101001 is also a match. On the other hand, 110001 is a mismatch match.
Continuous detection
Detect the sequences whenever they occur, and set dec to 1’b1
Please draw a state transition diagram in your report
A sample waveform is provided in the next page
I/O port definition
Input: clk, rst_n, in
Output: dec

Verilog Advanced Question 1 (Con’t)
A match case

A mismatch case

Verilog Advanced Question 2 (Con’t)
Traffic light controller Finite State Machine
Please complete the FSM in your report (some arrows are removed intentionally)

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A Traffic light controller “example” timing diagram is illustrated on the left
Please make sure that your state transitions follows the timing digram correctly
Verilog Advanced Question 2 (Con’t)

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Verilog Advanced Question 3
Greatest common divisor
Calculate the greatest common divisor of two numbers a and b
Top level block diagram and pseudo code are as follows
You shall not use loop statements and modulus (%) in your Verilog codes

Function gcd (a, b)
begin GCD pseudo
if (a == 0) code return b;
while (b != 0)
// Do the following operation once per clock cycle begin
if (a > b)
a = a – b;
else
b = b – a;
end
return a;
end 16

Verilog Advanced Question 3 (Cont’d)
Two cycles 17

Three states are used: WAIT, CAL, and FINISH
WAIT state
Wait for start == 1’b1 (one cycle) to begin the operation (and fetch the inputs)
CAL state
Perform the booth multiplication operations once per cycle Transition to FINSH state after 4 cycles of calculation.
FINISH state
Output the result p for one cycles
The state transition diagram of the booth multiplier
rst_n start=1’b1

Advanced Questions

Four options available: Coffee, Coke, Oolong, and Water
Prices are: Coffee (NT$ 75), Coke (NT$ 50), Oolong
(NT$ 30), Water (NT$ 25)
The rightmost three 7-segment displays show the money inserted into the machine
When rst_n == 1’b1, please display “0”
The maximum value is NT$ 100
Do not prepend ‘0’ when you only have one or two digits to display
Use five buttons to implement your design:
Left: NT$ 5
Center: NT$ 10
Right: NT$ 50
Top: rst_n
Bottom: Cancel
FPGA Demonstration 2

FPGA Demonstration 2
Use four LEDs to indicate which drinks you can buy
LED[3:0] corresponds to Coffee, Coke, Oolong, and Water, respectively
Use the keyboard to select which drinks you buy
‘a’, ’s’, ‘d’, ‘f’ corresponds to Coffee, Coke, Oolong, and Water, respectively
Assume that the machine allows you to buy ONLY ONE DRINK at a time
Use the rightmost three 7-segment display to show the rest of the money after buying a drink
E.g., if you inserted NT$ 40 and bought a can of Oolong (NT$ 30), the 7segment display will show NT$ 10
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FPGA Demonstration 2
Remember to add debounce and one-pulse circuits to your buttons
Decrement the 7-segment display by NT$ 5 every second to mimic the process of returning changes
Return the changes until it becomes zero
If the buyer does not want to buy a drink, he/she can use a Cancel Button to cancel it
The inserted money will be returned the same way (NT$ 5 per second)
RESET
The layout of the Insert buttons used in this NT$ 5 NT$ 50 question
Insert NT$ 10Insert
Cancel 25