Description

Lab 1: Gate-Level Verilog
Prof. Chun-Yi Lee
Agenda
Lab 1 Outline
Basic questions (1.5%)
Individual assignment
Only demonstration is necessary. Nothing to submit.
Demonstration on your FPGA board (In class)
Assignment submission (Submit to eeclass)
Source codes and testbenches
Lab report in PDF
Lab 1 Rules
Lab 1 Submission Requirements
Source codes and test benches
Please follow the templates EXACTLY
We will test your codes by TAs’ testbenches
Lab 1 report
Please submit your report in a single PDF file
Please draw the gate-level circuits of your designs Remember not to draw them by hands
Please explain your designs in detail
Please list the contributions of each team member clearly
Please explain how you test your design
What you have learned from Lab 1
Agenda
Basic Questions
Verilog Basic Question 1

Agenda
Advanced Questions
Group assignment
(Gate-level) 4-bit 1-to-4 de-multiplexer (DMUX)
(Gate-level) 4-bit simple crossbar switch with MUX/DMUX
(Gate-level) 4-bit 4x4crossbar with simple crossbar switch
(Gate-level) 1-bit toggle flip flop (TFF)
(Gate-level) 4-bit simple crossbar switch with MUX/DMUX
Verilog Advanced Question 1
(Gate-level) 4-bit 1-to-4 de-multiplexer (DMUX)
The value of the selected output is set to in, while others’ are set to 0.

control
Verilog Advanced Question 3
(Gate-level) 4-bit 4x4crossbar with simple crossbar switch
Please reuse your module in the previous question
Some configurations are not routable, please list them in your report

Verilog Advanced Question 4
(Gate-level) 1-bit toggle flip flop (TFF)
Please reuse your design of DFF, and avoid using XOR directly

Advanced Questions
Group assignment
(Gate-level) 4-bit 1-to-4 de-multiplexer (DMUX)
(Gate-level) 4-bit simple crossbar switch with MUX/DMUX
(Gate-level) 4-bit 4x4crossbar with simple crossbar switch
(Gate-level) 1-bit toggle flip flop (TFF)
(Gate-level) 4-bit simple crossbar switch with MUX/DMUX
FPGA Demonstration 1
(Gate-level) 4-bit simple crossbar switch with MUX/DMUX
Please implement your gate-level 4-bit simple crossbar switch with MUX/DMUX on
Agenda

Verilog Testbench
G1 module output Nand_Latch_1 (q, qbar, preset, clear); q, qbar; presetq input preset, clear;
Design
nand #1 G1 (q, preset, qbar),
G2 (qbar, clear, q);
endmodule clearqbar
G2
`timescale 1ns / 1ps // Simulation Unit / Accuracy module test_Nand_Latch_1; // Testbench module
reg preset, clear; // Inputs should be declared as reg wire q, qbar; // Outputs should be declared as wire Nand_Latch_1 M1 (q, qbar, preset, clear); // Instantiate YOUR DESIGN module
always begin // always condition: The description always happens
#20 clear = !clear; // The value of clear inverts every 20 ns
Testbench end
initial // Initial conditions
begin
preset = 1’b0; clear = 1’b1;
#10 // Units of “Simulation Units”. In this case, 10ns preset = 1’b1; end
endmodule