Description

Lab 2: Advanced Gate-Level Verilog
Prof. Chun-Yi Lee
Agenda
Lab 2 Outline
Lab 2 Rules
Lab 2 Submission Requirements
Source codes and testbenches
Please follow the templates EXACTLY
We will test your codes by TAs’ testbenches
Lab 2 report
Please submit your report in a single PDF file
Please draw the gate-level circuits of your designs (please use computer softwares to draw your figures)
Please explain your designs in detail
Please list the contributions of each team member clearly
Please explain how you test your design
What you have learned from Lab 2
Agenda
Basic Questions
Verilog Basic Question 1
(Gate Level) NAND gates only
Use NAND gates only to realize the following functions
NOT, NOR, AND, OR, XOR, XNOR, NAND
Input/Output: a (1bit), b (1bit), sel (3 bits), out (1 bit)
Please draw your circuits in your report

sel [2:0] out
000 out = a nand b
001 out = a and b
010 out = a or b
011 out = a nor b
100 out = a xor b
101 out = a xnor b
110 & 111 out = !a

Verilog Basic Question 3
(Gate Level) 1-bit full adder & half adder
Please design two modules: one for a 1-bit full adder and one for a 1-bit half adder, use NAND gates only
Please reuse the module of your majority gate for the 1-bit full adder design
Please explain the difference between these two adders in your report.
asum asum b
cincout bcout
Agenda
Advanced Questions
Group assignment
(Gate Level) 8-bit ripple carry adder (RCA)
(Gate Level) Decode and execute
(Gate Level) 8-bit carry-lookahead (CLA) Adder
(Gate Level) 4-bit multiplier
(Gate-level) An exhausted testbench design
Verilog Advanced Question 1
(Gate-level) 8-bit ripple-carry adder (RCA)
Instantiate the 1-bit full adder module from the Basic Question 3
a[7]b[7] a[6]b[6] a[1] b[1] a[0]b[0]

Verilog Advanced Question 2
(Gate Level) Decode and execute
Please use the universal gate depicted on the bottom left corner only to implement the basic logic gates listed below.
Please draw your circuits of your basic logic gates (AND, OR, NOT …) in your report Implement your universal gate in Universal_Gate.v and instantiate it in your design, do not submit this file and ensure that your design uses no primitive logic gates.
Use your own basic logic gate modules to realize the following functions specified in the table defined on the bottom-right corner
Input/Output: rs (4 bits), rt (4 bits), sel (3 bits), rd (4 bits)

Instruction OP_Code Function
ADD 000 rd = rs + rt
SUB 001 rd = rs – rt (hint: two’s complement)
out BITWISE AND 010 rd = rs (bitwise AND) rt
BITWISE OR 011 rd = rs (bitwise OR) rt
The universal gate RS CIR. LEFT SHIFT 100 rd = {rs[2:0], rs[3]} to be used
RT ARI. RIGHT SHIFT 101 rd = {rt[3], rt[3:1]}
COMPARE EQ 110 rd = {3’b111, rs == rt}
COMPARE GT 111 rd = {3’b101, rs > rt}
14
Verilog Advanced Question 3
Verilog Advanced Question 4
(Gate Level) 4-bit multiplier
Design a 4-bit unsigned multiplier using your full adder and half adder
Using NAND gates only
Please explain how it works
Please draw your block diagram using your adders and logic gates Inputs: a[3:0] and b[3:0]; Output: p[7:0]

a3 a2 a1 a0

“Carry”means × b3 b2 b1 b0
1’b0
p7 p6 p5 p4 p3 p2 p1 p0 16

Verilog Advanced Question 5
(Test Bench) An exhausted testbench design
In this question, please design a testbench for a 4-bit adder circuit
We will use faulty designs to check if your test bench can find the intentionally inserted errors
We will check whether all the input patterns are covered
Testbench requirements
Please follow the template for your test bench I/Os, which have two additional pins: error and done.
Please change input to the test instance every five nanoseconds.
One nanosecond after any input is given, set error to 1’b1 if an error is detected. Similarly, if no error is detected, set error back to 1’b0 one nanosecond ofter the input is given.
Set done to 1’b1 five nanoseconds after testing is finished.
Verilog Advanced Question 5 (Con’t)

Advanced Questions
Group assignment
(Gate Level) 8-bit ripple carry adder (RCA)
(Gate Level) Decode and execute
(Gate Level) 8-bit carry-lookahead (CLA) Adder
(Gate Level) 4-bit multiplier
(Gate-level) An exhausted testbench design
FPGA Demonstration 1